LL RCC Constants

LSE oscillator driving capability

group RCC_LL_EC_LSE

Defines

LL_RCC_LSEDRIVE_LOW 0U

Xtal mode lower driving capability

LL_RCC_LSEDRIVE_MEDIUMLOW RCC_RTCCR_LSEDRV_0

Xtal mode medium low driving capability

LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_RTCCR_LSEDRV_1

Xtal mode medium high driving capability

LL_RCC_LSEDRIVE_HIGH RCC_RTCCR_LSEDRV

Xtal mode higher driving capability

External LSE mode

group RCC_LL_EC_LSEEXT

Defines

LL_RCC_LSE_ANALOG_MODE 0U

ANALOG clock used as LSE external clock source

LL_RCC_LSE_DIGITAL_MODE RCC_RTCCR_LSEEXT

DIGITAL clock used as LSE external clock source

EXTERNAL HSE Mode

group RCC_LL_EC_HSEEXT

Defines

LL_RCC_HSE_ANALOG_MODE 0U

HSE clock used as ANALOG clock source

LL_RCC_HSE_DIGITAL_MODE RCC_CR1_HSEEXT

HSE clock used as DIGITAL clock source

LSCO Selection

group RCC_LL_EC_LSCO_CLKSOURCE

Defines

LL_RCC_LSCO_CLKSOURCE_LSI 0U

LSI selection for low speed clock

LL_RCC_LSCO_CLKSOURCE_LSE RCC_RTCCR_LSCOSEL

LSE selection for low speed clock

HSI kernel clock out divider factor

group RCC_LL_EC_HSIK

Defines

LL_RCC_HSIK_DIV_1 RCC_CR2_HSIKDIV_0

HSI kernel clock divided by 1

LL_RCC_HSIK_DIV_1_5 RCC_CR2_HSIKDIV_1

HSI kernel clock divided by 1.5

LL_RCC_HSIK_DIV_2 (RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 2

LL_RCC_HSIK_DIV_2_5 RCC_CR2_HSIKDIV_2

HSI kernel clock divided by 2.5

LL_RCC_HSIK_DIV_3 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 3

LL_RCC_HSIK_DIV_3_5 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1)

HSI kernel clock divided by 3.5

LL_RCC_HSIK_DIV_4 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 4

LL_RCC_HSIK_DIV_4_5 RCC_CR2_HSIKDIV_3

HSI kernel clock divided by 4.5

LL_RCC_HSIK_DIV_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 5

LL_RCC_HSIK_DIV_5_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_1)

HSI kernel clock divided by 5.5

LL_RCC_HSIK_DIV_6 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 6

LL_RCC_HSIK_DIV_6_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2)

HSI kernel clock divided by 6.5

LL_RCC_HSIK_DIV_7 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_0)

HSI kernel clock divided by 7

LL_RCC_HSIK_DIV_7_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1)

HSI kernel clock divided by 7.5

LL_RCC_HSIK_DIV_8 RCC_CR2_HSIKDIV

HSI kernel clock divided by 8

PSI kernel clock out divider factor

group RCC_LL_EC_PSIK

Defines

LL_RCC_PSIK_DIV_1 RCC_CR2_PSIKDIV_0

PSI kernel clock divided by 1

LL_RCC_PSIK_DIV_1_5 RCC_CR2_PSIKDIV_1

PSI kernel clock divided by 1.5

LL_RCC_PSIK_DIV_2 (RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 2

LL_RCC_PSIK_DIV_2_5 RCC_CR2_PSIKDIV_2

PSI kernel clock divided by 2.5

LL_RCC_PSIK_DIV_3 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 3

LL_RCC_PSIK_DIV_3_5 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1)

PSI kernel clock divided by 3.5

LL_RCC_PSIK_DIV_4 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 4

LL_RCC_PSIK_DIV_4_5 RCC_CR2_PSIKDIV_3

PSI kernel clock divided by 4.5

LL_RCC_PSIK_DIV_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 5

LL_RCC_PSIK_DIV_5_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_1)

PSI kernel clock divided by 5.5

LL_RCC_PSIK_DIV_6 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 6

LL_RCC_PSIK_DIV_6_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2)

PSI kernel clock divided by 6.5

LL_RCC_PSIK_DIV_7 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_0)

PSI kernel clock divided by 7

LL_RCC_PSIK_DIV_7_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1)

PSI kernel clock divided by 7.5

LL_RCC_PSIK_DIV_8 RCC_CR2_PSIKDIV

PSI kernel clock divided by 8

PSI target frequency configuration

group RCC_LL_EC_PSIFREQ

Defines

LL_RCC_PSIFREQ_100MHZ 0U

PSI output frequency is 100 MHz

LL_RCC_PSIFREQ_144MHZ RCC_CR2_PSIFREQ_0

PSI output frequency is 144 MHz

LL_RCC_PSIFREQ_160MHZ RCC_CR2_PSIFREQ_1

PSI output frequency is 160 MHz

PSI ref clock frequency selection

group RCC_LL_EC_PSIREF

Defines

LL_RCC_PSIREF_32768HZ 0U

PSI reference clock input is 32768 Hz

LL_RCC_PSIREF_8MHZ RCC_CR2_PSIREF_0

PSI reference clock input is 8 MHz

LL_RCC_PSIREF_16MHZ RCC_CR2_PSIREF_1

PSI reference clock input is 16 MHz

LL_RCC_PSIREF_24MHZ (RCC_CR2_PSIREF_1 | RCC_CR2_PSIREF_0)

PSI reference clock input is 24 MHz

LL_RCC_PSIREF_25MHZ RCC_CR2_PSIREF_2

PSI reference clock input is 25 MHz

LL_RCC_PSIREF_32MHZ (RCC_CR2_PSIREF_2 | RCC_CR2_PSIREF_0)

PSI reference clock input is 32 MHz

LL_RCC_PSIREF_48MHZ (RCC_CR2_PSIREF_2 | RCC_CR2_PSIREF_1)

PSI reference clock input is 48 MHz

LL_RCC_PSIREF_50MHZ RCC_CR2_PSIREF

PSI reference clock input is 50 MHz

PSI ref clock source selection

group RCC_LL_EC_PSIREFSRC

Defines

LL_RCC_PSISOURCE_HSE 0U

PSI source is HSE

LL_RCC_PSISOURCE_LSE RCC_CR2_PSIREFSRC_0

PSI source is LSE

LL_RCC_PSISOURCE_HSIDIV18 RCC_CR2_PSIREFSRC_1

PSI source is HSI divided by 18

System clock switch

group RCC_LL_EC_SYS_CLKSOURCE

Defines

LL_RCC_SYS_CLKSOURCE_HSIDIV3 0U

HSI DIV3 clock selection as system clock

LL_RCC_SYS_CLKSOURCE_HSIS RCC_CFGR1_SW_0

HSIS clock selection as system clock

LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1

HSE oscillator selection as system clock

LL_RCC_SYS_CLKSOURCE_PSIS RCC_CFGR1_SW

PSIS clock selection as system clock

System clock switch status

group RCC_LL_EC_SYS_CLKSOURCE_STATUS

Defines

LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3 0U

HSI DIV3 clock used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_HSIS RCC_CFGR1_SWS_0

HSIS clock used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1

HSE oscillator used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_PSIS RCC_CFGR1_SWS

PSIS clock used as system clock

AHB prescaler

group RCC_LL_EC_SYSCLK_DIV

Defines

LL_RCC_HCLK_PRESCALER_1 0U

SYSCLK not divided

LL_RCC_HCLK_PRESCALER_2 RCC_CFGR2_HPRE_3

SYSCLK divided by 2

LL_RCC_HCLK_PRESCALER_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 4

LL_RCC_HCLK_PRESCALER_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1)

SYSCLK divided by 8

LL_RCC_HCLK_PRESCALER_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 16

LL_RCC_HCLK_PRESCALER_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2)

SYSCLK divided by 64

LL_RCC_HCLK_PRESCALER_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 128

LL_RCC_HCLK_PRESCALER_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1)

SYSCLK divided by 256

LL_RCC_HCLK_PRESCALER_512 RCC_CFGR2_HPRE

SYSCLK divided by 512

SYSTICK clock source selection

group RCC_LL_EC_SYSTICK_CLKSOURCE

Defines

LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U

HCLKDIV8 clock used as SYSTICK clock source

LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR2_SYSTICKSEL_0

LSI clock used as SYSTICK clock source

LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR2_SYSTICKSEL_1

LSE clock used as SYSTICK clock source

APB low-speed prescaler (APB1)

group RCC_LL_EC_APB1_DIV

Defines

LL_RCC_APB1_PRESCALER_1 0U

HCLK not divided

LL_RCC_APB1_PRESCALER_2 RCC_CFGR2_PPRE1_2

HCLK divided by 2

LL_RCC_APB1_PRESCALER_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0)

HCLK divided by 4

LL_RCC_APB1_PRESCALER_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1)

HCLK divided by 8

LL_RCC_APB1_PRESCALER_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)

HCLK divided by 16

APB high-speed prescaler (APB2)

group RCC_LL_EC_APB2_DIV

Defines

LL_RCC_APB2_PRESCALER_1 0U

HCLK not divided

LL_RCC_APB2_PRESCALER_2 RCC_CFGR2_PPRE2_2

HCLK divided by 2

LL_RCC_APB2_PRESCALER_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0)

HCLK divided by 4

LL_RCC_APB2_PRESCALER_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1)

HCLK divided by 8

LL_RCC_APB2_PRESCALER_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)

HCLK divided by 16

APB high-speed prescaler (APB3)

group RCC_LL_EC_APB3_DIV

Defines

LL_RCC_APB3_PRESCALER_1 0U

HCLK not divided

LL_RCC_APB3_PRESCALER_2 RCC_CFGR2_PPRE3_2

HCLK divided by 2

LL_RCC_APB3_PRESCALER_4 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_0)

HCLK divided by 4

LL_RCC_APB3_PRESCALER_8 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1)

HCLK divided by 8

LL_RCC_APB3_PRESCALER_16 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1 | RCC_CFGR2_PPRE3_0)

HCLK divided by 16

System clock selection after a wakeup from system Stop

group RCC_LL_EC_STOP_WAKEUPCLOCK

Defines

LL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 0U

HSIDIV3 selection after wake-up from STOP

LL_RCC_STOP_WAKEUPCLOCK_HSIS RCC_CFGR1_STOPWUCK

HSIS selection after wake-up from STOP

MCO1 SOURCE selection

group RCC_LL_EC_MCO1SOURCE

Defines

LL_RCC_MCO1SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | 0x00000000U)

SYSCLK selection as MCO1 source

LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_0)

HSE selection as MCO1 source

LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1)

LSE selection as MCO1 source

LL_RCC_MCO1SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0)

LSI selection as MCO1 source

LL_RCC_MCO1SOURCE_PSIK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2)

PSI kernel clock selection as MCO1 source

LL_RCC_MCO1SOURCE_HSIK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_0)

HSI kernel clock selection as MCO1 source

LL_RCC_MCO1SOURCE_PSIS (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2| RCC_CFGR1_MCO1SEL_1)

PSIS selection as MCO1 source

LL_RCC_MCO1SOURCE_HSIS (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0 )

HSIS selection as MCO1 source

MCO2 SOURCE selection

group RCC_LL_EC_MCO2SOURCE

Defines

LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | 0x00000000U)

SYSCLK selection as MCO2 source

LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_0)

HSE selection as MCO2 source

LL_RCC_MCO2SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1)

LSE selection as MCO2 source

LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1| RCC_CFGR1_MCO2SEL_0)

LSI selection as MCO2 source

LL_RCC_MCO2SOURCE_PSIK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2)

PSI kernel clock selection as MCO2 source

LL_RCC_MCO2SOURCE_HSIK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_0)

HSI kernel clock selection as MCO2 source

LL_RCC_MCO2SOURCE_PSIDIV3 (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_1)

PSI DIV 3 selection as MCO2 source

LL_RCC_MCO2SOURCE_HSIDIV3 (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_1 | RCC_CFGR1_MCO2SEL_0 )

HSI DIV 3 selection as MCO2 source

MCO1 prescaler

group RCC_LL_EC_MCO1_DIV

Defines

LL_RCC_MCO1SOURCE_NOCLOCK (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | 0x00000000U)

MCO1 output disabled, no clock on MCO1

LL_RCC_MCO1_PRESCALER_1 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0)

MCO1 not divided

LL_RCC_MCO1_PRESCALER_2 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_1)

MCO1 divided by 2

LL_RCC_MCO1_PRESCALER_3 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1)

MCO1 divided by 3

LL_RCC_MCO1_PRESCALER_4 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2)

MCO1 divided by 4

LL_RCC_MCO1_PRESCALER_5 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_0)

MCO1 divided by 5

LL_RCC_MCO1_PRESCALER_6 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1)

MCO1 divided by 6

LL_RCC_MCO1_PRESCALER_7 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0)

MCO1 divided by 7

LL_RCC_MCO1_PRESCALER_8 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3)

MCO1 divided by 8

LL_RCC_MCO1_PRESCALER_9 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_0)

MCO1 divided by 9

LL_RCC_MCO1_PRESCALER_10 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1)

MCO1 divided by 10

LL_RCC_MCO1_PRESCALER_11 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0)

MCO1 divided by 11

LL_RCC_MCO1_PRESCALER_12 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2)

MCO1 divided by 12

LL_RCC_MCO1_PRESCALER_13 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_0)

MCO1 divided by 13

LL_RCC_MCO1_PRESCALER_14 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1)

MCO1 divided by 14

LL_RCC_MCO1_PRESCALER_15 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE)

MCO1 divided by 15

MCO2 prescaler

group RCC_LL_EC_MCO2_DIV

Defines

LL_RCC_MCO2SOURCE_NOCLOCK (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | 0x00000000U)

MCO2 output disabled, no clock on MCO2

LL_RCC_MCO2_PRESCALER_1 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0)

MCO2 not divided

LL_RCC_MCO2_PRESCALER_2 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_1)

MCO2 divided by 2

LL_RCC_MCO2_PRESCALER_3 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1)

MCO2 divided by 3

LL_RCC_MCO2_PRESCALER_4 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2)

MCO2 divided by 4

LL_RCC_MCO2_PRESCALER_5 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_0)

MCO2 divided by 5

LL_RCC_MCO2_PRESCALER_6 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1)

MCO2 divided by 6

LL_RCC_MCO2_PRESCALER_7 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_0)

MCO2 divided by 7

LL_RCC_MCO2_PRESCALER_8 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3)

MCO2 divided by 8

LL_RCC_MCO2_PRESCALER_9 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_0)

MCO2 divided by 9

LL_RCC_MCO2_PRESCALER_10 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_1)

MCO2 divided by 10

LL_RCC_MCO2_PRESCALER_11 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_0)

MCO2 divided by 11

LL_RCC_MCO2_PRESCALER_12 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2)

MCO2 divided by 12

LL_RCC_MCO2_PRESCALER_13 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_0)

MCO2 divided by 13

LL_RCC_MCO2_PRESCALER_14 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1)

MCO2 divided by 14

LL_RCC_MCO2_PRESCALER_15 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE)

MCO2 divided by 15

RTC clock source selection

group RCC_LL_EC_RTC_CLKSOURCE

Defines

LL_RCC_RTC_CLKSOURCE_NONE 0U

No clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_LSE RCC_RTCCR_RTCSEL_0

LSE oscillator clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_LSI RCC_RTCCR_RTCSEL_1

LSI oscillator clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_RTCCR_RTCSEL

HSE oscillator clock divided by RTCPRE used as RTC clock

Peripheral USARTx clock source selection

group RCC_LL_EC_USARTx_CLKSOURCE

Defines

LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, 0UL)

PCLK2 clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_0)

PSIK clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_1)

HSIK clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL)

LSE clock used as USART1 clock source

LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, 0UL)

PCLK1 clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_0)

PSIK clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_1)

HSIK clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL)

LSE clock used as USART2 clock source

LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, 0UL)

PCLK1 clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_0)

PSIK clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_1)

HSIK clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL)

LSE clock used as USART3 clock source

Peripheral UARTx clock source selection

group RCC_LL_EC_UARTx_CLKSOURCE

Defines

LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, 0UL)

PCLK1 clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_0)

PSIK clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_1)

HSIK clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL)

LSE clock used as UART4 clock source

LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, 0UL)

PCLK1 clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_0)

PSIK clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_1)

HSIK clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL)

LSE clock used as UART5 clock source

Peripheral LPUART clock source selection

group RCC_LL_EC_LPUART_CLKSOURCE

Defines

LL_RCC_LPUART1_CLKSOURCE_PCLK3 0U

PCLK3 clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_HSIK RCC_CCIPR1_LPUART1SEL_0

HSIK clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR1_LPUART1SEL_1

LSE clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_LSI RCC_CCIPR1_LPUART1SEL

LSI clock used as LPUART1 clock source

Peripheral SPIx clock source selection

group RCC_LL_EC_SPIx_CLKSOURCE

Defines

LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, 0UL)

PCLK2 clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL_0)

PSIK clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL_1)

HSIK clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_AUDIOCLK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL)

AUDIOCLK clock used as SPI1 clock source

LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, 0UL)

PCLK1 clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL_0)

PSIK clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL_1)

HSIK clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_AUDIOCLK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL)

AUDIOCLK clock used as SPI2 clock source

LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, 0UL)

PCLK1 clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL_0)

PSIK clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL_1)

HSIK clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_AUDIOCLK LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL)

AUDIOCLK clock used as SPI3 clock source

Peripheral FDCAN clock source selection

group RCC_LL_EC_FDCAN_CLKSOURCE

Defines

LL_RCC_FDCAN_CLKSOURCE_PCLK1 0U

PCLK1 clock used as FDCAN clock source

LL_RCC_FDCAN_CLKSOURCE_PSIS RCC_CCIPR1_FDCANSEL_0

PSIS clock used as FDCAN clock source

LL_RCC_FDCAN_CLKSOURCE_PSIK RCC_CCIPR1_FDCANSEL_1

PSIK clock used as FDCAN clock source

LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR1_FDCANSEL

HSE clock used as FDCAN clock source

Peripheral I2Cx clock source selection

group RCC_LL_EC_I2Cx_CLKSOURCE

Defines

LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, 0UL)

PCLK1 clock used as I2C1 clock source

LL_RCC_I2C1_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, RCC_CCIPR2_I2C1SEL_0)

PSIK clock used as I2C1 clock source

LL_RCC_I2C1_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, RCC_CCIPR2_I2C1SEL_1)

HSIK clock used as I2C1 clock source

LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, 0UL)

PCLK1 clock used as I2C2 clock source

LL_RCC_I2C2_CLKSOURCE_PSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, RCC_CCIPR2_I2C2SEL_0)

PSIK clock used as I2C2 clock source

LL_RCC_I2C2_CLKSOURCE_HSIK LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, RCC_CCIPR2_I2C2SEL_1)

HSIK clock used as I2C2 clock source

Peripheral I3C clock source selection

group RCC_LL_EC_I3C_CLKSOURCE

Defines

LL_RCC_I3C1_CLKSOURCE_PCLK1 0U

PCLK1 clock used as I3C1 clock source

LL_RCC_I3C1_CLKSOURCE_PSIK RCC_CCIPR2_I3C1SEL_0

PSIK clock used as I3C1 clock source

LL_RCC_I3C1_CLKSOURCE_HSIK RCC_CCIPR2_I3C1SEL_1

HSIK clock used as I3C1 clock source

Peripheral ADCDAC clock source selection

group RCC_LL_EC_ADCDAC_CLKSOURCE

Defines

LL_RCC_ADCDAC_CLKSOURCE_HCLK 0U

HCLK clock used as ADCDAC clock source

LL_RCC_ADCDAC_CLKSOURCE_PSIS RCC_CCIPR2_ADCDACSEL_0

PSIS clock used as ADCDAC clock source

LL_RCC_ADCDAC_CLKSOURCE_PSIK RCC_CCIPR2_ADCDACSEL_1

PSIK clock used as ADCDAC clock source

LL_RCC_ADCDAC_CLKSOURCE_HSIK RCC_CCIPR2_ADCDACSEL

HSIK clock used as ADCDAC clock source

ADCDAC prescaler

group RCC_LL_EC_ADCDAC_PRESCALER

Defines

LL_RCC_ADCDAC_PRESCALER_1 0U

ADC and DAC kernel clock not divided

LL_RCC_ADCDAC_PRESCALER_2 RCC_CCIPR2_ADCDACPRE_0

ADC and DAC kernel clock divided by 2

LL_RCC_ADCDAC_PRESCALER_4 RCC_CCIPR2_ADCDACPRE_1

ADC and DAC kernel clock divided by 4

LL_RCC_ADCDAC_PRESCALER_8 (RCC_CCIPR2_ADCDACPRE_1 | RCC_CCIPR2_ADCDACPRE_0)

ADC and DAC kernel clock divided by 8

LL_RCC_ADCDAC_PRESCALER_16 (RCC_CCIPR2_ADCDACPRE_2)

ADC and DAC kernel clock divided by 16

LL_RCC_ADCDAC_PRESCALER_32 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_0)

ADC and DAC kernel clock divided by 32

LL_RCC_ADCDAC_PRESCALER_64 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_1)

ADC and DAC kernel clock divided by 64

LL_RCC_ADCDAC_PRESCALER_128 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_1 | RCC_CCIPR2_ADCDACPRE_0)

ADC and DAC kernel clock divided by 128

DAC1 Sample and hold clock source selection

group RCC_LL_EC_DAC1SH_CLKSOURCE

Defines

LL_RCC_DAC1SH_CLKSOURCE_LSE 0U

LSE clock used as DAC1 clock source

LL_RCC_DAC1SH_CLKSOURCE_LSI RCC_CCIPR2_DACSEL

LSI clock used as DAC1 clock source

Peripheral LPTIM clock source selection

group RCC_LL_EC_LPTIM_CLKSOURCE

Defines

LL_RCC_LPTIM1_CLKSOURCE_PCLK3 0U

PCLK3 clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_HSIK RCC_CCIPR2_LPTIM1SEL_0

HSIK clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR2_LPTIM1SEL_1

LSE clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL

LSI clock used as LPTIM1 clock source

Peripheral USBFS (48MHz) clock source selection

group RCC_LL_EC_CK_CLKSOURCE

Defines

LL_RCC_CK48_NONE 0U

CK48 clock source disable

LL_RCC_CK48_CLKSOURCE_PSIDIV3 RCC_CCIPR2_CK48SEL_0

PSI_DIV_3 clock used as CK48 clock source

LL_RCC_CK48_CLKSOURCE_HSIDIV3 RCC_CCIPR2_CK48SEL_1

HSI_DIV_3 clock used as CK48 clock source

LL_RCC_CK48_CLKSOURCE_HSE RCC_CCIPR2_CK48SEL

HSE clock used as CK48 clock source

Peripheral USARTx get clock source

group RCC_LL_EC_USARTx

Defines

LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, 0UL)

USART1 Clock source selection

LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, 0UL)

USART2 Clock source selection

LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, 0UL)

USART3 Clock source selection

Peripheral UARTx get clock source

group RCC_LL_EC_UARTx

Defines

LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, 0UL)

UART4 Clock source selection

LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, 0UL)

UART5 Clock source selection

Peripheral LPUART get clock source

group RCC_LL_EC_LPUART

Defines

LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR1_LPUART1SEL

LPUART1 Clock source selection

Peripheral SPIx get clock source

group RCC_LL_EC_SPIx

Defines

LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, 0UL)

SPI1 Clock source selection

LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, 0UL)

SPI2 Clock source selection

LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR1 , (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, 0UL)

SPI3 Clock source selection

Peripheral FDCAN get clock source

group RCC_LL_EC_FDCAN

Defines

LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL

FDCAN Clock source selection

Peripheral I2Cx get clock source

group RCC_LL_EC_I2Cx

Defines

LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, 0UL)

I2C1 Clock source selection

LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE ( RCC_OFFSET_CCIPR2 , (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, 0UL)

I2C2 Clock source selection

Peripheral I3C get clock source

group RCC_LL_EC_I3C

Defines

LL_RCC_I3C1_CLKSOURCE RCC_CCIPR2_I3C1SEL

I3C1 Clock source selection

Peripheral ADCDAC get clock source

group RCC_LL_EC_ADCDAC

Defines

LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR2_ADCDACSEL

ADCDAC Clock source selection

Peripheral DAC1SH get clock source

group RCC_LL_EC_DAC1

Defines

LL_RCC_DAC1SH_CLKSOURCE RCC_CCIPR2_DACSEL

DAC1SH Clock source selection

Peripheral LPTIM get clock source

group RCC_LL_EC_LPTIM

Defines

LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR2_LPTIM1SEL

LPTIM1 Clock source selection

Peripheral USBFS (48MHz) get clock source

group RCC_LL_EC_CK

Defines

LL_RCC_CK48_CLKSOURCE RCC_CCIPR2_CK48SEL

CK48 Clock source selection

RCC Flags

group RCC_LL_FLAGS

Defines

LL_RCC_IT_LSIRDY RCC_CIFR_LSIRDYF

LSI ready interrupt flag

LL_RCC_IT_LSERDY RCC_CIFR_LSERDYF

LSE ready interrupt flag

LL_RCC_IT_HSIRDY RCC_CIFR_HSISRDYF

HSIS ready interrupt flag

LL_RCC_IT_HSIDIV3RDY RCC_CIFR_HSIDIV3RDYF

HSIDIV3 ready interrupt flag

LL_RCC_IT_PSIDIV3RDY RCC_CIFR_PSIDIV3RDYF

PSIDIV3 ready interrupt flag

LL_RCC_IT_HSIKRDY RCC_CIFR_HSIKRDYF

HSIK ready interrupt flag

LL_RCC_IT_PSIRDY RCC_CIFR_PSISRDYF

PSIS ready interrupt flag

LL_RCC_IT_PSIKRDY RCC_CIFR_PSIKRDYF

PSIK ready interrupt flag

LL_RCC_IT_HSERDY RCC_CIFR_HSERDYF

HSE ready interrupt flag

LL_RCC_IT_HSECSS RCC_CIFR_HSECSSF

HSE clock security system interrupt flag

LL_RCC_IT_LSECSS RCC_CIFR_LSECSSF

LSE clock security system interrupt flag

RCC Secure/Privilege/Lock/Public attributes

group RCC_LL_EC_ATTRIBUTES

Defines

LL_RCC_ATTR_NPRIV 0UL

Non-privileged attribute

LL_RCC_ATTR_PRIV 1UL

Privileged attribute

RCC Privilege Attribute Items

group RCC_LL_EC_PRIV_ITEMS

Defines

LL_RCC_PRIV_ITEM_ALL RCC_PRIVCFGR_PRIV

Peripheral XSPI clock source selection

Note

This section is not available for STM32C562xx.

Peripheral ETH1 clock source selection

Note

This section is not available for STM32C562xx.

ETH1 prescaler

Note

This section is not available for STM32C562xx.

Peripheral XSPI1 get clock source

Note

This section is not available for STM32C562xx.

Peripheral ETH1 get clock source

Note

This section is not available for STM32C562xx.